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Freescale Semiconductor Application NoteWhite Paper

Document Number: ANnnnn Rev. 0.1, 09/2009

DDR/mDDR Calibration Procedure for i.MX51
by Amir Zaltzman AP departme

nt Freescale Semiconductor, Inc. Isreal

This paper describes the calibration procedure that is required in order to find the optimal delay line settings for the i.MX51 for working with DDR2 or Mobile DDR memories. These delay line settings determine at which point of time each of the DQS lines will sample the corresponding data lines. This procedure is required to be used to find the corresponding delay values per board reference design or a product - as different delays and capacitances are introduced and different memory devices may be used. After the correct settings are found on few typical units and compared to have more or less the same values, they can be used across the same type of board package or product. Note: It is recommended to read the DDR controller (ESDCTLv2) chapter in the i.MX51 Reference Manual before reading this paper in order to get familiar with eSDCTLv2 functionality and programming model.

1. 2. 3. 4. 5.

Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Delay line calibration . . . . . . . . . . . . . . . . . . . . . . . . . 2 DQS gating calibration . . . . . . . . . . . . . . . . . . . . . . . 10 Single-ended/differential mode selection . . . . . . . . . 14 DDR calibration procedure - summary . . . . . . . . . . . 15

Freescale Semiconductor, Inc., 2008. All rights reserved. Preliminary—Subject to Change Without Notice

Introduction

1

Introduction

The goal of the calibration procedure is to align the DQS edges, which sample the data, to the mid point of the steady data window (which changes with respect to the DDR clock period rate). This DQS alignment is required for both read and write. In addition, for DDR2 memories, a DQS gating calibration is required. The reason is as follows: DDR2 memories are using differential DQS lines with On Die Termination and do not have on board pull up/down resistors on the DQS lins. This means that during a read operation, when a DQS line is not driven at all, a 'high Z' value could propagate to the DDR controller and be miss-interprated as an access. Therefore, the DQS signals need to be gated internally and used only when needed. This is what is done by DQS calibration procedure. For mDDR memories, pull-down resistors can be used on the DQS lines and hence DQS lines always have a defined value, so there is no need to gate them. It is recommended to perform the calibration with VCC=1.2V (although it's not a stated requirement).

2

Delay line calibration

The concept of the delay calibration is similar for both read and write. The main difference is that for read, the DQS to DQ timing is relative to the MX51 internally. For the write cycle, the DQS to DQ timing is relative to the DDR memory device. As shown in Figure 1, the goal is to find the center of the "valid sample window" which meets the setup and hold time requirements. The example code of the delay line calibration can be found in compass at: TBD - place the location here. .

valid data

DQS DQ

Figure 1. DQ and DQS timing

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Delay line calibration

window center Left boundary Right boundary valid sample window Tsetup Thold

DQS

DQ

Figure 2. DQ and DQS timing - zoom in

2.1

Delay line registers

There are 5 DQS lines (4 for read and 1 for write) and hence there are 5 delay line registers in the ESDCTLv2 module: Four registers control the delay of the DQS signal for read. One register controls the delay of the data bus for write. 1. Register ESDCDLY1 – at address 0x83fd9020 – controls the delay of DQS[0] for read - data bits[7:0]. 2. Register ESDCDLY2 – at address 0x83fd9024 – controls the delay of DQS[1] for read - data bits[15:8]. 3. Register ESDCDLY3 – at address 0x83fd9028 – controls the delay of DQS[2] for read - data bits[23:16]. 4. Register ESDCDLY4 – at address 0x83fd902c – controls the delay of DQS[3] for read - data bits[31:24]. 5. Register ESDCDLY5 – at address 0x83fd9030 – controls the delay of all the data bus for write - data bits[31:0]. The delay line register is configured by 2 parameters: DLY_ABS_OFFSET_# is the amount of delay added, normalized by one DDR clock period. It maintains the same delay between DQS and data by taking into account the changes in process and operating conditions of the i.MX51 silicon. For example, if a value of 128 ( cycle) is programmed, it means it will include the amount of delay units that are needed to provide a cycle delay. The number of delay untils will automatically change depending on temperature, voltage and silicon case to keep the constant delay of of DDR clock cycle. DLY_OFFSET_# is the amount of physical delay units added. The delay of the units varies between different parts and across different operating conditions.

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Delay line calibration

2.2

Calculation of delay parameters for the delay lines

The delay for each delay line is calculated according to the following formula - (see equation below) where: "measure" is the amount of delay units in one DDR clock period, this parameter is calculated by hardware. "512" represents the maximum number of time steps within 1 DDR clock period. DLY_ABS_OFFSET_# is set to 128 by default which is equivalent to cycle DLY_OFFSET_# is set to -12 by default to compensate for the constant delay of 12 units1.

(measure) ×

DLY_ABS_OFFSET_5 + DLY_OFFSET_5 = Total_delay 512

"Total_delay" represents the number of delay units that are used for Delay Line 5 (write delay line). It takes into account the measurement that is performed by the measurement unit and adds the delay programmed in ESDCDLY5 register. The value of "Total_delay" is represented by ESDGPR[7:0] register (bit field is called QTR_CYCLE_LENGTH) at address 0x83fd9034. The "measure" value can be found by a simple calculation from the above formula and it is used for both read and write delay calculations. The delay for the 4 "read delay lines" follows the exact formula as above using the corresponding parameters from ESDCDLY1,2,3,4 registers. The total delay ("Total_delay" parameter) is only reflected for the "write delay line". The recommended method to find the calibration parameters for the write and read delay lines is to find the optimal DLY_ABS_OFFSET values, without using DLY_OFFSET (remains at default of -12). This reduces the sensitivity to changes in PVT conditions, as the delays are defined as fractions of a cycle. NOTE: A value of DLY_ABS_OFFSET_# is not directly tanslated into the number of physical delay units , it depends on the silicon speed and the DDR frequency. The maximum number of delay units per cycle when running at 100Mhz on best case silicon is 512. This means that at 200Mhz and on typical silicon, approximately 2-5 consecutive values of DLY_ABS_OFFSET_# may provide the same number of delay units.

1. A constant delay of 12 delay unit exists by default between each DQS lines and the data lines for both read and write. This an internal delay in the design and cannot be removed.
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Delay line calibration

2.2.1

DLY_ABS_OFFSET_#

The DLY_ABS_OFFSET – bits[15:8] allows values in the range of [0:255], but the total equation (Total_delay) is bounded between 0 (actually, it means 12 delay units which is the minimum) and half the DDR clock period delay. The example below explains how the DLY_ABS_OFFSET_# value is actually translated to delay in silicon. So if, for example - "Total_delay" result that is reflected by ESDGPR[7:0] bits is 24. - The DDR frequency is set to 200MHz (5ns period). - The DLY_OFFSET_5 is set to its default value (i.e. -12) - The DLY_ABS_OFFSET_5 is set to its default value (i.e. 128) Then:
512 x (Total_delay + DLY_OFFSET_5) DLY_ABS_OFFSET_5

measure =

measure result is 144, which means that each delay unit is adds about 35ps in silicon (period/measure=5ns/144=~35ps). Then: - The amount of delay introduced due to DLY_ABS_OFFSET_5 is: (144)x(128/512)= 36 delay units. In case the this delay is 12 or less, "Total_delay" value will be read as zero which corresponds to the minimum delay applied by the constant 12 units. From this point onward in this document, when referring to a delay, a delay window or delay line settings, the meaning is the DLY_ABS_OFFSET value (bits [15:8] of the ESDCDLY1,2,3,4,5 registers ).

2.3

Delay line calibration procedure
NOTE The code of the calibration procedure must be placed in internal memory and should not be placed in external memory (DDR), since delay line values are not configured yet.

The calibration procedure consists of steps for finding the write and read values using a check function.

2.3.1

The check function

The check whether the programmed delay values are good or not is done by a generic function that accesses the DDR (both CS0 and CS1).
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Delay line calibration

The function's role is to give an indication whether the current delay line settings are valid. The test executed by this function should be stressful enough to give a good indication whether the delay line settings are valid. yet, it shouldn't take too long since this function will be called several thousands of times in the calibration procedure - see estimations for write and read in .2.3.2.1 and 2.3.2.2. The function should perform write bursts, single writes, read bursts, single reads, 8/16/32 bit accesses and access different address spaces. Other masters, such as SDMA, can also be used to stress the DDR. The function should write the data both the DDR and to another address space in the chip (ex. IRAM, GMEM). This way, when the data is read from the DDR, it can be compared to the golden data stored in the internal memory. The function should have one input [mask] and one output [pass or fail]. The mask input is used to determine which byte (0,1,2 or 3) is about to be compared. Since each read delay line register controls one byte of data, only one byte at a time can be checked. The status returns PASS if all the data that is read back from the DDR passes the comparison with the golden data. If there is at least one data (data that is checked with the relevant mask) that is incorrect, the function returns FAIL. ex. check_ddr(int mask) ….. return status There are 2 types of check functions: 1.An aggressive check function that performs a large number of accesses to wide address range. This function is used for fine tuning for finding the actual delay values. 2.A less aggressive function, called "typical" check function with reduced number of access to a narrower address range. This function is used for quicker search for finding the initial values that will be used later on by the aggressive function.

2.3.2

Procedure steps

First thing to do is set bit 11 to 1'b1 in the ESDMISC register (0x83fd9010). This bit (FRC_MSR bit) requests the delay line circuitry to constantly perform measurements and calculate the delay line values based on the parameters in ESDCDLYx registers. Therefore, during the entire calibration procedure, this bit has to be set. The procedure starts with finding the delay value for write delay line, and afterwords finding the delay line values for the read. For DDR2 memory, the delay calibration needs to be performed when DQS lines and memory are configured to single-ended mode, and not differential. This will get rid of the dependency of the DQS gating when the delay of DQS lines is moved around during calibration.
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Delay line calibration

2.3.2.1

Finding "write" delay value

The basic algorithm for finding the delay value for the write delay line is shown below. The detailed steps will be described later on. 1.Find "point zero". 2.Search for the largest target read window for byte0 while scanning all byte0 read delay values and write delay values. 3.Repeat step 2 for byte1, byte2, byte3. 4.Check if target read windows are valid. 5.Find the center of each target read window. 6.Using the read windows that were found, find the target write window. 7.Check if target write window is valid. 8.Find the true write window. 9.Check that write window is valid. 10.Find the center of the write window.

Detailed steps of the algorithm: 1.Find the largest value of DLY_ABS_OFFSET_5 that still provides zero delay (12 constant delay units): This is done by decreasing the value of DLY_ABS_OFFSET_5 and reading the value of "Total_delay" each time, till it reaches zero. The value is recorded as "point zero". It will be used as the smallest value of DLY_ABS_OFFSET_# when searching the left boundary of the write and read valid sample windows later on. 2.Search for a read window per DQS line: Starting with byte 0 (for DQS 0). For each read delay value of DLY_ABS_OFFSET_1 search for at least one working write delay value. If no working write delay value is found, the value of DLY_ABS_OFFSET_1 will not be part of the window. This is done as follows: For each value of DLY_ABS_OFFSET_1, starting from "point zero" and up till the maximum value (255), increasing the value by 5 each time (this saves time by not going through all values but still provides good resolution), search for at least one working write value - also by going over values of DLY_ABS_OFFSET_5 starting from "point zero" and up till the maximum value (255), increasing the value by 5 each time. For each set of values, invoke the "typical" check function with selection of byte 0 only. The result is the read window that will be used to find the write delay values - later on in step 6. See Figure 3 below for information on how a window is defined. 3.Repeat step 2 for byte1, byte2 and byte3 (in case of 32bit memory), using the corresponding DLY_ABS_OFFSET_# field. The result is a read delay window per byte (DQS line). These windows will
i.MX51, Rev. 0.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 7

Delay line calibration

be used as target read windows when searching for the read delay window later on in Section 2.3.2.2, "Finding "read" delay value. 4.Check that the read windows are wide enough to allow some margin accross process corners and different boards of the same type. If the window that is found is too narrow, there may be a problem with the board design. 5.Find the center of each of the read windows. These are the read delay values which will be used to find the write delay window. 6.Finding a target write window: Program the read delay values that were found. Starting from "point zero" increase the value of DLY_ABS_OFFSET_5 by 5 (and up till the maximum value - 255) and invoke the "typical" check function. Select the largest window, as shown in Figure 4. The result is a write delay window that will be used as a target write window using the "aggressive" check function. 7.Check that the target write window is a valid sample window, as done in step 4. If it is a valid window, continue to the next step. If no valid window is found, try the calibration on few different parts. If the issue persists on multiple parts, there may be a problem with the board design. 8.Finding the true write window: Program the same read delay values as in step 6. Go through all values from the target write window beginning at start point -4 till the end point +4 (since we skipped every 5 points), increase the value of DLY_ABS_OFFSET_5 by 1 each time and invoke the "aggressive" check function. This provides the true write window. 9.Check that write window is a valid sample window, as done in step 4. If it is a valid window, continue to the next step. If no valid window is found, try the calibration on few different parts. If the issue persists on multiple parts, there may be a problem with the board design. 10.The center of the window is calculated and used as the newly calculated DLY_ABS_OFFSET_5 value for the write delay line. Finding target windows for read and write A target window is window that is being found by using the "typical" check function. This window is used as a target to be checked later on by the "aggressive" check function (which finds the true window). When searching for target windows, a working window is defined as the largest number of successful consecutive values, as shown in Figure 3.

point zero

"potential" target window 255 read/write delay values X X X X X X X X X

X

"failing" point "passing" point

Figure 3. A working window

i.MX51, Rev. 0.1 8 Preliminary—Subject to Change Without Notice Freescale Semiconductor

Delay line calibration

The target window is selected by taking the largest working window that was found. This is done for read (per each byte) and for write, as shown in Figure 4.
point zero write delay values

255

read delay values

selected target read window

selected target write window

255

Figure 4. Selecting the target window

The estimated number of iterations is as follows: Assuming "point zero" is between DLY_ABS_OFFSET_# value of 50 to 60. Hence there are total of ~200 (out of 255) valid values. When we use the "typical" check function we skip 5 each time, therefore there are ~40 values to check per each delay line. When checking a read delay value, we search write delay values till we find a successfull access. This means that maximum of 40 write delay values will be searched (in case of failure). In other cases, the number could be much less. Therefore, for the target read window, the maximum number of iterations is: 40 (write delay) x 40 (read delay) x number_of_bytes For 4 bytes we get: 1600x4=6400 Afterwards, for the target write window there additional 40 iterations, hence the "typical" function is being invoked less than 6440 times. Assuming there will be around 100 values in the target write window, the "aggressive" check function will be invoked 100 times.
i.MX51, Rev. 0.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 9

DQS gating calibration

2.3.2.2

Finding "read" delay value

The read delay values are calibrated after the write values were found and programmed in DLY_ABS_OFFSET_5. Hence, it is assumed that data is written correctly and the failures are due to improper read delay values. The following steps are used to find the delay values for the read delay lines: 1.For byte0, go through all values from the target read window, found in step 3 of the detailed description in section 1 for finding the write delay value (detailed description) . Beginning at start point -4 till the end point +4, increase the value of DLY_ABS_OFFSET_1 by 1 each time and invoke the "aggressive" check function with selection of byte0 only. This provides the true read window for DQS 0. 2.Repeat step 1 for each byte. 3.Check that the windows that are found are wide enough. If all values are valid, continue to the next step. If the windows that were found are too narrow, try the calibration on few different parts. If the issue persists on multiple parts, there may be a problem with the board design. 4.The center of each window is calculated and used as the newly calculated DLY_ABS_OFFSET_# values for the read delay lines.

The estimated number of iterations is as follows: Assuming there will be around 100 values per each target read window, the "aggressive" check function will be invoked around 400 times. Once all of the 5 delay values are known, the calibration process is finished and the FRC_MSR bit can be set back to 0.

3

DQS gating calibration

The purpose of the DQS gating calibration is to align the rise of the internal DQS gating signal to be in the preamble period of the incoming DQS burst. When differential mode is used for the DQS lines when using DDR2 memories, no pull up/down are applied to the DQS lines. Therefore, the value of the DQS line is 'high z' in non-active periods. In Figure 5 the DQS is propagated as 'high z' into the design since the enable signal is raised too early. In Figure 6, the DQS signal is wrapped by the DQS enable signal.

i.MX51, Rev. 0.1 10 Preliminary—Subject to Change Without Notice Freescale Semiconductor

DQS gating calibration

high 'z'

preamble period

DQS DQS enable

Figure 5. DQS gating - DQS enable is not aligned

high 'z'

preamble period

DQS DQS enable

Figure 6. DQS gating - after calibration

During the DQS gating calibration procedure, the DQS enable signal is moved around (with resolution of a quarter cycle of the DDR clock period) to get the delay that is required to properly wrap the DQS signal. The calibration is done for each of the 4 DQS read signals. Part of the delay is commonly configured for all, but fine tuning is done for each line separately. The example code of the DQS gating calibration can be found in compass at: TBD - place the location here.

3.1

DQS gating register

The delay parameters of the gating signals for the 4 read DQS lines are configured in ESDGPR register (General Purpose Register) at address: 0x83fd9034 of the ESDCTLv2 module. ESDGPR[31] - DIG_EN bit: DQS in enable bit. This bit must be set when using differential DQS signals. ESDGPR[30:29] - DIG_CYC: Delay in cycles, common to all 4 DQS lines. ESDGPR[28:27] - DIG_QTR: Delay in cycles, common to all 4 DQS lines. ESDGPR[26:25] - DIG_OFF0: Delay in cycles for DQS 0. ESDGPR[24:23] - DIG_OFF1: Delay in cycles for DQS 1.
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DQS gating calibration

ESDGPR[22:21] - DIG_OFF2: Delay in cycles for DQS 2. ESDGPR[20:19] - DIG_OFF3: Delay in cycles for DQS 3. Register ESDCTMISC[1] - RST bit (at address 0x83fd9034) is used to reset the ESDCTLv2 module during the calibration of the DQS gating signals.

3.2

Calculation of delay parameters for the DQS gating

During the calibration procedure of the DQS gating, it is assumed that the read and write delay lines are calibrated as previously described. NOTE The code of the calibration procedure must be placed in internal memory and should not be placed in external memory (DDR), since delay for the DQS enable lines is not configured yet. The calibration is done by writing expected data to memory, and performing read (read with a burst) each time with a different delay settings per byte (per DQS enable line). Starting from delay zero per byte, the delay is increased till the read is performed correctly. After the delay per each byte is found, an additional cycle delay is added to each DQS enable line in order to move it further into the preamble period. The maximum skew that can be configured between the DQS lines is 3/4 cycle. It is assumed that the required delay for each DQS enable line is nearly the same as the others, and hence this skew should be enough. delay0,1,2,3 are internal variables that hold a cycle delay value per each DQS enable line and are used for the calculations. They are incremented each time and used to calculate the common delay and the specific offset per each DQS line. The sequence is done as following: 1. Write pre-defined data to DDR memory. 2. set delay0,delay1,delay2,delay3 to 0 3. read data per each byte: If byte0 is wrong -> increment delay0 by 1 If byte1 is wrong -> increment delay1 by 1 If byte2 is wrong -> increment delay2 by 1 If byte3 is wrong -> increment delay3 by 1 If all are correct (all bytes read correct data) jump to step 7 4.Perform a software reset- it is done by setting RST bit to 1 and setting it back to 0. This is required to reset the pointers, since the wrong reads have made the FIFO pointers to become invalid. 5.Write new values to ESDGPR register to the following fields accordingly:

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DQS gating calibration

min_delay = min(delay0,delay1,delay2,delay3); -> Internal variable that holds the minimum delay, this will be the common delay. DIG_CYC = min_delay / 4; -> common delay in number of full cycles. DIG_QTR = min_delay % 4; -> Modulo of the minimum delay will give the remaining common delay in cycles. DIG_OFF0 = delay0 - min_delay; -> This is the remaining offset in cycles for the enable line of DQS0. DIG_OFF1 = delay1 - min_delay; -> This is the remaining offset in cycles for the enable line of DQS1. DIG_OFF2 = delay2 - min_delay; -> This is the remaining offset in cycles for the enable line of DQS2. DIG_OFF3 = delay3 - min_delay; -> This is the remaining offset in cycles for the enable line of DQS3. 6.Jump to step 3. 7. Increment delay0, delay1, delay2, delay3 by 1 to move the DQS enable signals further into the preamble period. 8. write new values to ESDGPR register. 9. Read data (all bytes) to check that read is still correct.

i.MX51, Rev. 0.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 13

Single-ended/differential mode selection

4

Single-ended/differential mode selection

The calibration for read and write delay values should be done at single-ended mode. For the DQS gating calibration, need to switch to differential mode.

4.1

Setting differential mode

The following steps are required to work at differential mode: 1.Setting the memory to differential DQS by using LMR command. 2.Setting the DQS pads of i.MX51 to differential mode - ESDMISC register in ESDCTLv2, DIFF_DQS_EN bit 3.Removing pull-ups and put-downs for DQS and DQS_B pads by configuring registers I IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 in the IOMUXC.

4.2

Setting single-ended mode

The following steps are required to work at single-ended mode: 1.Setting the memory to single ended DQS by using LMR command. 2.Setting the DQS pads of i.MX51 to single ended mode - ESDMISC register in ESDCTLv2, DIFF_DQS_EN bit 3.Adding pull-downs for DQS pads by configuring registers IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 in the IOMUXC. 4.Disable ODT in memory and for the i.MX51 IO pads - ESDMISC registers- TERM_CTLn bits, ODT_EN bit.

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DDR calibration procedure - summary

5

DDR calibration procedure - summary

The required steps for calibration when using DDR2 memories are: 1.Set to single-ended mode. 2.Perform calibration for write and read delay parameters. 3.Set to differential mode. 4.Perform calibration for the DQS gating. For MDDR memories, only need to perform calibration for write and read delay parameters

i.MX51, Rev. 0.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 15

DDR calibration procedure - summary

i.MX51, Rev. 0.1 16 Preliminary—Subject to Change Without Notice Freescale Semiconductor

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Document Number: ANnnnn Rev. 0.1 09/2009

Preliminary—Subject to Change Without Notice

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