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DFM


DFM Overview
?What is DFM
?Why to develop DFM

?How to do DFM

ZongMing lee MAY16, 2005

What is DFM

DFM is Design For Manufacture

Why to develop DFM

?

Reduce opportunity for error (FEMA) Reduce Design Complexity Reduce opportunity for process induced damage Ensure detection capabilities (increased test coverage) Utilize cost based trade-off analysis to manage divergent requirements

?

?

?

?

How to do DFM
?

Review DFM check list one by one,then Identify and drive Design issues Make DFM and tracking open issue
Develop DFMEA and tracking open issue

?

?

How to do DFM (step 1)
Review DFM check list one by one in NPI every stage Identify and drive Design issues

New model stage

Model CheckList
EVT DVT
P/L Rev: 0R PCB Rev.X11 Prod. Rev.X02-04

PILOT RUN
P/L Rev: 01 PCB Rev. A Prod. Rev.A00

Product Revision Information
Sectio n Item Ch eck co n ten ts 1 0.5D,0.8D跳線PITCH 是否為5~20mm . 2 所有元件料號是否為"7"開頭 跳線是否全為AI加工. 1/8W,1/4W,1/2W,1W(S)電阻呈臥式 ,Pitch是否Layout為5~17.5mm PCB板的靠板邊5mm內是否未LAYOUT SMD元件. PCB板板邊5mm有SMD處板邊是否開撈槽. RI植件小藍色,黃色陶瓷電容,電解電容PITCH是否為5mm 本體尺寸小于10*16mm(直徑*高度)的電解電容是否RI植件 PITCH為5mm,帶狀本體尺寸小于16mm(高度)的立式電阻是否RI植件 AI,RI,SMD植件元件的位置是否為0度或90度 AI,RI植件元件來料包裝方式是否為帶狀。 AI RI 元件腳徑與PCB孔徑是否為0.5mm腳徑匹配1.0mm孔徑。 AI RI 元件腳徑與PCB孔徑是否為0.8mm腳徑匹配1.2mm孔徑。 SMD IC元件其本体長邊是否與過錫爐方向垂直 SMD電容周圍是否無手插需剪腳元件 SMD的本體大小是否PCB對應的PAD大小一致,如0603,0805,1206等匹配 多腳的IC附近1.5mm范圍內是否無LAYOUT 其它小的SMD元件 PCB的銅箔面是否有供TE測試ICT的針點. (for lead free product) 3 4 5 6 7 8 AI,RI&SMD 9 10 11 12 13 14 15 16 17 18 Prep ared b y :

P/L Rev: 0G PCB Rev.X4 Prod. Rev. X00-05

Y

N

NA

Y

N

NA

Y

Check item

ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ

ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ

Identify and drive Design issues

Checked by:

How to do DFM (step 2)
Make DFM , Tracking open issue

PS-2142-1D DFM ( Design For Manufacturing Review ) Date: 3/1/2005

Customer: DELL N o

Stage:DVT3

Input Q'ty:100PCS Verification / Remarks

Problem

Corrective Action

Responsible

Date

Stage

Time Saving

1

INLET上FG線焊點頂住 RV101&L103,易將熱縮套管頂 破,有HI-POT不良隱患. S3小板上connector有傾斜現 象,導致S3插入MB后有傾斜 浮高現象 C628被Q701(穿過SADDLE) 線材頂住,受應力,有電性不良 隱患.

建議更改加工方式,旋轉成90焊 接.

趙啟聖

旋轉成90焊接

DVT1

2

繼續STUDY

趙啟聖

制作治具克服

DVT1

3 4 5

請STUDY,RELAYOUT PCB

林俊宏 圣

趙啟 黃啟昌

OPEN

DVT3

Follow DFM form to make DFM

Open issue must be close before MP

How to do DFM (step 3)
Develop PFMEA and tracking open issue
PRODUCT FAILURE MODE EFFECT ANALYSIS ( 失效模式影響度分析 )
Model Name: PS-2142-1D DVT3 PCB Rev:X11 Team Member
QC:

Customer :DELL Part List Rev: 0R Occurrence Ranking
1.Remote chance ---- < 0.01% 1

HI Date:3/1/04 Customer Spec Rev:X02-04 Severity/Effect Ranking
1.No negative impact to quality

QTY: 100Pcs Schematic Rev: X14 Detection Ranking Pages 1/1 Remark
7. Hard to be detected once in peocess,manual inspection

Wlin Wang

1.Certain to be detected for 100%

O=Ocurrence

D=Detection

S=Serverity

SAFETY: JF Li

2.Very low ------------ 0.01 ~ 0.1 %

2.Increase less operating time : <15sec 3.Increase more operating time: > 15sec 4.Inconvenience in Fit / Cosmetic 5.Specification Deviation

2. Easy to be detected with tools or instruments,readily for evidence 3. Easy to be detected with tools or instruments,slips by unoticed 4. Difficult to be detected twice in process even with tools or instruments 5. Difficult to be detected once in process even with tools or instruments
6. Hard to be detected twice in peocess,manual inspection

8.Failure detected may destroy the unit 9. Hve change of recurrence after detection 10.Slips by undetected with reliability possible

RPN=O*S*D

DQE:

CX Wang Lan Hu

3.Moderate

----------- 0.1 ~ 1 %

RPN=Risk Prior number

AI:

4.High --------------------1

~ 5%

To take action when RPN >144

ME/PE MFG: TE/IE:

Richard/Soldier YP Ji DavisLee/Richard ZA Deng Benson Lin/CS Chao

5.Almost Certain --------- 5 ~ 100 %

6.Customer Reject of Fit or Cosmetic 7.Function failure 8.Totally dysfunctional 9.Presents injury hazard 10.Fatal if used

RPN-----Top row of the risk assesment column for before improvement. RPN-----Bottom row of the risk assesment column for after improvement.

P/T Signature E/E: 趙啟聖 ME: 林俊宏 CAD: 張美姿

RM: P&T:

序號

工程名稱

故障模式

故障影響

影響 度

發生 度

檢出 度

RPN

建議改善對策

負責人

對策回覆日期及狀況

階段

No.

Name of Process

Potential Failure Mode

Effect of Potential Failure Potential electric risk will exist in PSU when the transistor was fastened a little slanting.

S'TY

F/O

DET.

Suggest Corrective Action

Res.

RD Action respond/due day

Stage

1

HP

The gap between metal part on D552 with heat sink 12.

9 0

5 1

Suggest to update the insulator spec to enlarge it. =E18*F18*G18 9 Approved by: Micro Shu

7

315

CS Chao

OK

DVT3

Prepared by:Richard Wang

Checked by:Zongmin Lee

Follow PFMEA form to make PFMEA

Remark: Open issue must be close before MP

The End

THANKS!


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