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Low Power Design of Pipelined ADC for Power Line Baseband Communication


龙源期刊网 http://www.qikan.com.cn Low Power Design of Pipelined ADC for Power Line Baseband Communication 作者:Yang Chen Xuejing Liu 来源:《电子世界》2013 年第 04 期 Abstract:This paper presents a 10bit 5MS/s pipelined analog-to-digital converter(ADC)for single carrier power line communication transceiver.It’s a low-power method by using switched op amp technique,and proposes the switch capacitor(SC)bias circuitry to solve the startup issue of the current bias.Two common-mode feedback networks are employed to solve the problem of common-mode stability.Removes the sample and hold circuitry(SHA)to further reduce power consumption.Simulation result shows that the proposed ADC achieves 9.6 ENOB,75.8dB SFDR.The power consumption is 0.6 mA for 1.8V supply voltage. Index Terms:Pipelined ADC;switched op amp;switch capacitor bias;SHA-less 1.Introduction The proposed pipelined ADC is used in single carrier power line communication system.The carrier frequency is 132 KHz and maximum sampling frequency should be supported to 5 MHz .Recently,low-power pipelined ADC design is mainly focused on the following aspects: sample and hold circuit removing technique[1],op amp sharing[2],digital background calibration[3].Sample and hold circuit removing configuration is suitable for low frequency application.Digital background calibration technique is useful for high-speed,high resolution and deep submicron process,such as 65 nm[3].For180nm process,as well as low-speed,mediumaccuracy pipelined ADC,the power consu

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