ECE 545 Project 3 Specification
System to be implemented Using high-level behavioral VHDL describe an 8-bit microcontroller MC68HC11E9, working in a single-chip mode, with the following simplifications: 1. Inputs and outputs of the microcontroller are reduced to clk, reset, PORTB, and PORTC. 2. Internal registers are reduced to the registers A, B, SP, CC (Condition Codes NZVC), and PC. 3. Internal I/O registers are limited to PORTB at the memory address $1004 PORTC at the memory address $1003 DDRC at the memory address $1007
4. Instruction set of the microcontroller is reduced to the following instructions a. Data transfer instructions LDAA, LDAB, LDS, STAA, STAB, STS b. Arithmetic instructions ADDA, ADDB, SUBA, SUBB c. Logic instructions ANDA, ANDB, ORAA, ORAB, EORA, EORB d. Data test instructions CMPA, CMPB e. Control instructions BEQ, BNE, BSR, RTS f. Stack instructions PSHA, PSHB, PULA, PULB
5. Addressing modes of the microcontroller are reduced to the following modes a. immediate b. extended c. inherent d. relative 6. Program is stored in the internal ROM starting at the address $D000 7. After reset, PC is set to the address $D000. 8. The only parts of 68HC11E9 implemented in your model are: a. CPU b. RAM (512 B in the range $0000-$01FF) c. ROM (12 kB in the range $D000-$FFFF) d. parallel I/O (PORTB and PORTC)
Features of the model 1. Your model should allow cycle accurate modeling of the circuit behavior. 2. Your model should contain debugging features equivalent to the debugging features of the DLX model, discussed in class and described in Ashenden, Chapter 15. 3. Generic parameters passed to the model should include a. name of the file with the contents of the internal ROM b. clk-to-output delay c. debugging mode 4. Your model should report all undefined opcodes, treat them as NOP, and proceed to the next ROM address.
Testing and debugging The behavior of your model should be carefully verified using a testbench instantiating your model with a. the internal ROM containing a valid program composed of a substantial subset of instructions implemented in the model b. debugging mode set to the most detailed mode (trace_each_step)
Deliverables 1. All source code files. 2. Contents of the internal ROM used for the model verification, in the hexadecimal notation, and expressed using the corresponding 68HC11 assembly language mnemonics. 3. The detailed log/report generated by your model for a given contents of ROM, and with the debugging mode set to trace_each_step.
Useful Resources 68HC11 E-series Reference Guide and if necessary 68HC11 E-series Technical Data 68HC11 Reference Manual all available at http://www.technologicalarts.com/myfiles/links.html Optionally: Peter Spasov, Microcontroller Technology, any edition, Prentice-Hall, Chapter II, Software. (you can borrow this book from the ECE 447 students).
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