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Area-Efficient Low Power CMOS Image Sensor Readout Circuit with Fixed Pattern Noise Cancellation_论文

Tran s. Tian jin Univ. 2 01 0 , 1 6: 34 2- 3 47 DOI 10 .1 00 7/ s 1 22 09 -0 10 -14 63 -6 Area-Efficient Low Powe r CM OS Im age Sensor Readout Circuit with Fixed Patt ern Noise Cancellation * ZHAO S hibin( 赵士彬) ,YAO S uying( 姚素英) ,NIE Ka im ing( 聂凯明) ,XU J ia ngt a o( 徐江涛) ( School of Electronic Information Engineering, Tianjin University, Tianjin 300072, China) Tianjin University and Springer-Verlag Berlin Heidelberg 2010 Ab stract :A low cost of die area and power consumption CMOS image sensor readout circuit with fixed pattern noise ( FPN) cancellation is proposed. By using only one coupling capacitor and switch in the double FPN cancelling correlative double sampling (CDS) , pixel FPN is cancelled and column FPN is stored and eliminated by the sampleand-hold operation of digitally programmable gain amplifier ( DPGA) . The bandwidth balance technology based on operational amplifier ( op-amp) sharing is also introduced to decrease the power dissipation of traditional multi-stage switched capacitor DPGA. The circuit is designed and simulated using 1P6M 0.18 m 1.8 V/3.3 V process. Simulation results indicate that the proposed CDS scheme can achieve an FPN of less than 1 mV. The total sampling capacitor per column is 0.9 pF and no column-wise power is dissipated. The die area and FPN value are cut by 70% and 41% respectively compared with amplifier-based CDS. The op-amp sharing gain stage can achieve a 12-bit precision and also implement an 8-bit gain controlling within a gain range of 24 dB. Its power consumption is 1.4 mW, which is reduced by 57% compared with traditional schemes. The proposed readout circuit is suitable for the application of low power cost-sensitive imaging systems. Keyword s :imaging system; image sensor; low power electronic; capacitor; operational amplifier; fixed pattern noise; bandwidth balance technology; op-amp sharing During the last decade, CMOS image sensors ( CIS) have been recognized as a competitive alternative to the charge -coupled device ( CCD ) due to its high integration and low power consumption[ 1-3]. In the traditional architecture of CIS, the readout circuit usually contains a correlative double sampling ( CDS) [4] and digitally programmable gain amplifier ( DPGA ) [5] . The former samples the reset and signal voltage, and suppresses the reset noise and pixel-to- pixel fixed pattern noise ( FPN ) ; the latter amplifies the CDS output with a gain controlled by the peripheral circuit of CIS to achieve some functio

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